Job Talk : Impact of Fiber Weaves On the Electrical Performance of Glass Epoxy Packages

12 Mar 2018, 15:00
Dr. Ahmet C. Durgun

Impact of Fiber Weaves On the Electrical Performance of Glass Epoxy Packages

Today’s microelectronics manufacturing industry is facing several challenges as the market marches towards smaller form factor and higher bandwidth products. One of the key challenges associated with these devices is to achieve the necessary electrical performance with sufficiently low-cost packaging solutions. In order to minimize packaging costs, engineers continuously attempt to shrink the size of the package, which imposes a set of challenges on maintaining the electrical performance. Furthermore, the ever-increasing bus speeds drive increasingly stringent requirements on the current and next-generation high-speed communication channels, both at the system and component levels. Some of the low-cost packaging technologies utilize glass epoxy substrates that are composed of glass fiber bundles and epoxy resin, which have different electrical properties. These differences result in variations in characteristic impedance and propagation speeds, which may be detrimental at high data rates. The insertion loss, within-pair skew, differential to common mode conversion ratio, and crosstalk of transmission lines may drastically increase due to the fiber weave effect. Consequently, the link budget of high-speed communication channels may be significantly hindered. In this seminar, the package level impact of fiber weaves on the electrical performance of high-speed buses will be addressed, in the light of current microelectronic demands, and some mitigation techniques will be discussed.



Ahmet Cemal Durgun received the B.S.E.E. and M.S.E.E. degrees from Middle East Technical University, Turkey, Ankara, in 2005 and 2008, respectively, where he completed the double major program in mathematics and received the B.S. degree, in 2006. He completed his Ph.D. studies, related to flexible antennas and high impedance surfaces, at Arizona State University, Tempe, AZ, USA, in 2013. Currently, he is with the Intel Corporation, Assembly and Test Technology Development Department, working as a Sr. Analog Engineer. His research interests include microelectronic packaging, design of high-speed communication channels, high routing density interconnects, signal integrity, and applied electromagnetics.